Texas Instruments TMS320C6201 Reference Manual page 106

Synchronization: Triggering DMA Transfers
Table 5–6. Synchronization Events (Continued)
5.6.1 Latching of DMA Channel Event Flags
5-18
Event Number
Event Acronym
(Binary)
01010 DMA_INT2
01011 DMA_INT3
01100 XEVT0
01101 REVT0
01110 XEVT1
01111 REVT1
10000 DSPINT
10001 XEVT2
10010 REVT2
Other Reserved
The DMA channel secondary control register (described in Table 5–4) con-
tains STAT and CLR fields for read and write synchronization (RSYNC and
WSYNC) events.
Latching of DMA Synchronization Events: A low-to-high transition (or high-to-
low transition when selected by WSPOL or RSPOL) of the selected event is
latched by each DMA channel. The occurrence of this transition causes the asso-
ciated STAT field to be set in the DMA channel secondary control register. If no
synchronization is selected, the STAT bit is always read as 1. A single event can
trigger multiple actions.
User Clearing and Setting of Events: By clearing pending events before
starting a block transfer, you can force the DMA channel to wait for the next
event. Conversely, by setting events before starting a block transfer, you can
force the synchronization events necessary for the first element transfer. You
can clear or set events (and thus the related STAT bit) by writing 1 to the corre-
sponding CLR or STAT field, respectively. Writing a 0 to either of these bits has
no effect. Also, the CLR bits are always read as 0 and have no associated stor-
age. Separate bits for setting or clearing are provided to allow clearing of some
bits without setting others and vice versa. Your user manipulation of events
has priority over any simultaneous automated setting or clearing of events.
Event Description
DMA channel 2 interrupt
DMA channel 3 interrupt
McBSP 0 transmit event
McBSP 0 receive event
McBSP 1 transmit event
McBSP 1 receive event
Host processor to DSP interrupt
McBSP 2 transmit event
McBSP 2 receive event