Texas Instruments TMS320C6201 Reference Manual page 461

cache RAM 4-3
chaining EDMA channels by an event 6-34
Channel Chain Enable Register (CCER),
figure 6-35
channel chain enable register (CCER) 6-6, 6-34
Channel Interrupt Enable Register (CIER),
figure 6-32
channel interrupt enable register (CIER) 6-6, 6-32
Channel Interrupt Pending Register (CIPR),
figure 6-32
channel interrupt pending register (CIPR) 6-6, 6-32
channel/event entry 6-13
channels 6-36
chaining 6-34
chip enable (CE) spaces 4-18
circular buffering 6-25
clean a range of address from the L2 4-23
clean operation 4-21
CLKRM 11-60
clock output enabling 9-64
clock source selection 12-8
communication between the host device
and the CPU 8-7
companding data format 11-51
companding hardware 11-50
nonDLB method 11-52
companding internal data 11-51
complex sorting, circular buffering 6-25
conditions, serial port exception 11-41
conditions for linking 6-26
configuration
element length 11-28
frame and clock 11-23
frame length 11-27
multiprocessor 15-11
serial port 11-7
configuration of the interrupt selector 13-10
connector
14-pin header 15-2
dimensions, mechanical 15-12
DuPont 15-3
contention on the data bus 8-10
contiguous elements 6-5
control and status register (CSR) 2-3, 4-6, 4-9
control pins, SDRAM 9-23
control register boundary conditions 12-11
control registers 1-9, 4-2, 8-4, 9-5, 9-6, 9-9
EDMA 6-6
control status register 3-4
figure iii
controller 2-3
data memory 1-6
direct memory access 1-6
DMA 2-1
DMA controller 5-4
L2 4-22
peripheral bus 1-8
program memory 2-2, 9-5
count events 12-2
counting 12-8
CPU, core 1-5
CPU control status register 3-5
CPU interrupts 11-22
CPU servicing of EDMA interrupts 6-34
CPU write to the ESR 6-17
CPU–initiated EDMA 6-17
CPU–initiated EDMA transfers 6-7, 6-17
CSR, figure iii
cycle description 8-36
D
data, invalidating in the L1D 4-12
data access controller 1-9, 8-4
data address 4-3
data and program memories 1-6
data bus, HD 7-7
data cache control (DCC) 4-9
data cache controller 4-3
data cache mode settings 4-10
data clock generation 11-57
bit clock 11-58
CLKRM 11-60
CLKSM 11-57, 11-60
frame synchronization 11-58
input clock source mode 11-57
receive clock selection 11-60
data delay 11-30
figure 11-30
data latches 7-5
data memory 3-2
internal 1-6
Index
Index-3