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Data Transmission and Reception
11.3.2.2 Transmit Ready Status: XEVT, XINT, and XRDY
11.3.3 CPU Interrupts: (R/X)INT
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data has been read by either the CPU or the DMA controller, RRDY is cleared
to 0. Also, at device reset or serial port receiver reset (RRST = 0), the RRDY
is cleared to 0 to indicate that no data has yet been received and loaded into
DRR. RRDY directly drives the McBSP receive event to the DMA controller
(via REVT). Also, the McBSP receive interrupt (RINT) to the CPU can be driv-
en by RRDY if RINTM = 00b (default value) in the SPCR.
XRDY = 1 indicates that the DXR contents have been copied to XSR and that
DXR is ready to be loaded with a new data word. When the transmitter transi-
tions from reset to non-reset (XRST transitions from 0 to 1), XRDY also transi-
tions from 0 to 1 indicating that the DXR is ready for new data. Once new data
is loaded by the CPU or the DMA controller, XRDY is cleared to 0. However,
once this data is copied from the DXR to the XSR, XRDY transitions again from
0 to 1. The CPU or the DMA controller can write to DXR although XSR has not
yet been shifted out on DX. XRDY directly drives the transmit synchronization
event to the DMA controller (via XEVT). Also, the transmit interrupt (XINT) to
the CPU can be driven by XRDY if XINTM = 00b (default value) in the SPCR.
The receive interrupt (RINT) and transmit interrupt (XINT) signal the CPU of
changes to the serial port status. Four options exist for configuring these inter-
rupts. These options are set by the receive/transmit interrupt mode field,
(R/X)INTM, in the SPCR. The possible values of the mode and the configura-
tions they represent are:
(R/X)INTM = 00b. Interrupt on every serial element by tracking the
(R/X)RDY bits in the SPCR.
(R/X)INTM = 01b. Interrupt at the end of a subframe (16 elements or less)
within a frame. See subsection 11.6.3.3 for details.
(R/X)INTM = 10b. Interrupt on detection of frame synchronization pulses.
This generates an interrupt even when the transmitter/receiver is in reset.
This is done by synchronizing the incoming frame sync pulse to the CPU
clock and sending it to the CPU via (R/X)INT. See subsection 11.5.3.4 for
more information.
(R/X)INTM = 11b. Interrupt on frame synchronization error. Note that if any
of the other interrupt modes are selected, (R/X)SYNCERR may be read
when servicing the interrupts to detect this condition. See subsections
11.3.7.2 and 11.3.7.5 for more details on synchronization error.
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