Texas Instruments TMS320C6201 Reference Manual page 260

EMIF Registers
Table 9–5. EMIFtoSDRAMControlRegisterFieldDescription
9-16
Field Description
TRC Specifies the t
TRC = t
RC
TRP Specifies the t
/ p § – 1
TRP = t
RP
TRCD Specifies the t
TRCD = t
RCD
INIT Forces initialization of all SDRAM present
INIT = 0: no effect
INIT = 1: initialize SDRAM in each CE space configured for SDRAM
RFEN Refresh enable
RFEN = 0: SDRAM refresh disabled
RFEN = 1: SDRAM refresh enabled
SDWID † † SDRAM width select
SDWID = 0: Each external SDRAM space consists of four 8-bit SDRAMs
SDWID = 1: Each external SDRAM space consists of two 16-bit SDRAMs
SDCSZ ‡ ‡ SDRAM column size
SDCSZ = 00: 9 column address pins
SDCSZ = 01: 8 column address pins
SDCSZ = 10: 10 column address pins
SDCSZ = 11: reserved
SDRSZ ‡ ‡ SDRAM column size
SDCSZ = 00: 11 row address pins
SDCSZ = 01: 12 row address pins
SDCSZ = 10: 13 row address pins
SDCSZ = 11: reserved
SDBSZ ‡ ‡ SDRAM bank size
SDBSZ = 0: two banks
SDBSZ = 1: four banks
† Applies to 'C6201/C6202/C6701
‡ Applies to 'C6211/C6711
§ p – refers to the EMIF clock period, which is equal to CLKOUT2 period for the
'C6201/C6202/C6701, or ECLKOUT period for the 'C6211/C6711
value of the SDRAM
RC
/ p § – 1
value of the SDRAM in CLKOUT2 cycles
RP
value of the SDRAM in CLKOUT2 cycles
RCD
/ p § – 1