Texas Instruments TMS320C6201 Reference Manual page 357

11.3.6.2 Data Packing using Frame Sync Ignore Bits
Figure 11–22. Maximum Frame Frequency Operation With 8-Bit Data
CLKR
FSR
DR
CLKX
FSX
DX
DXR-to-XSR copy
Section 11.3.4.6 describes one method of changing the element length and frame
length to simulate 32-bit serial element transfers, thus requiring much less bus
bandwidth than four 8-bit transfers require. This example works when there are
multiple elements per frame. Now consider the case of the McBSP operating at
maximum packet frequency, as shown in Figure 11–22. Here, each frame has on-
ly a single 8-bit element. This stream takes one read transfer and one write trans-
fer for each 8-bit element. Figure 11–23 shows the McBSP configured to treat this
stream as a continuous stream of 32-bit elements. In this example, (R/X)FIG is
set to 1 to ignore unexpected subsequent frames. Only one read transfer and one
write transfer is needed every 32-bits. This configuration effectively reduces the
required bus bandwidth to one-fourth of the bandwidth needed to transfer four
8-bit blocks.
Element 1
RBR-to-DRR copy RBR-to-DRR copy
DXR-to-XSR copy
Element 2 Element 3
RBR-to-DRR copy
DXR-to-XSR copy
Multichannel Buffered Serial Ports
Data Transmission and Reception
Element 4
RBR-to-DRR copy
DXR-to-XSR copy
11-39