Synchronization Events - Texas Instruments TMS320C6201 Reference Manual

5.6 Synchronization: Triggering DMA Transfers
Table 5–6. Synchronization Events
Synchronization allows DMA transfers to be triggered by events such as inter-
rupts from internal peripherals or external pins. Three types of synchronization
can be enabled for each channel:
Read synchronization: Each read transfer waits for the selected event to
occur before proceeding.
Write synchronization: Each write transfer waits for the selected event to
occur before proceeding.
Frame synchronization: Each frame transfer waits for the selected event
to occur before proceeding.
Selection of Synchronization Events: The events are selected by the RSYNC
and WSYNC fields in the DMA channel primary control register. If FS = 1 in this
register, then the event selected by RSYNC enables an entire frame, and
WSNYC must be set to 00000b. If a channel is set up to operate in split mode
(SPLIT 00b), RSYNC and WSYNC must be set to non-zero values. Up to 31
events are available. If the value of these fields is set to 00000b, no synchroniza-
tion is necessary. In this case, the read, write, or frame transfers occur as soon
as the resource is available to that channel. The association between values in
these fields and events is shown in Table 5–6. This is similar to the fields in the
interrupt selector (see section 13.4, Configuring the Interrupt Selector ). The dif-
ferences are that the McBSP generates separate interrupts and DMA synchro-
nization events and that the DSPINT is located differently in the encoding.
Event Number
(Binary)
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
Synchronization: Triggering DMA Transfers
Event Acronym
None
TINT0
TINT1
SD_INT
EXT_INT4
EXT_INT5
EXT_INT6
EXT_INT7
DMA_INT0
DMA_INT1
Direct Memory Access (DMA) Controller
Event Description
No synchronization
Timer 0 interrupt
Timer 1 interrupt
EMIF SDRAM timer interrupt
External interrupt pin 4
External interrupt pin 5
External interrupt pin 6
External interrupt pin 7
DMA channel 0 interrupt
DMA channel 1 interrupt
5-17