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Programmable Clock and Framing
11.5.2.3 Bit Clock Polarity: CLKSP
11.5.2.4 Bit Clock and Frame Synchronization
11-58
The external clock (CLKS) is selected to drive the sample rate generator clock
divider by selecting CLKSM = 0. In this case, the CLKSP bit in the SRGR
selects the edge of CLKS on which sample rate generator data bit clock
(CLKG) and frame sync signal (FSG) are generated. Since the rising edge of
CLKSRG generates CLKG and FSG, the rising edge of CLKS when CLKSP
= 0 or the falling edge of CLKS when CLKSP = 1 causes the transition on CLKG
and FSG.
When CLKS is selected to drive the sample rate generator (CLKSM = 0),
GSYNC can be used to configure the timing of CLKG relative to CLKS. GSYNC
= 1 ensures that the McBSP and the external device to which it is communicat-
ing are dividing down the CLKS with the same phase relationship. If GSYNC =
0, this feature is disabled and CLKG runs freely and is not resynchronized. If
GSYNC = 1, an inactive-to-active transition on FSR triggers a resynchronization
of CLKG and the generation of FSG. CLKG always begins at a high state after
synchronization. Also, FSR is always detected at the same edge of CLKS that
generates CLKG, regardless of the length the FSR pulse. Although an external
FSR is provided, FSG can still drive internal receive frame synchronization
when GSYNC = 1. When GSYNC = 1, FPER is a don't care, because the frame
period is determined by the arrival of the external frame sync pulse.
Figure 11–40 and Figure 11–41 show this operation with various polarities of
CLKS and FSR. These figures assume that FWID is 0, for a FSG = 1 CLKG
wide.
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