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11.3.7.2 Unexpected Receive Frame Synchronization: RSYNCERR
Figure 11–26 shows the decision tree that the receiver uses to handle all incom-
ing frame synchronization pulses. The diagram assumes that the receiver has
been activated (RRST = 1). Unexpected frame sync pulses can originate from
an external source or from the internal sample rate generator. An unexpected
frame sync pulse is defined as a sync pulse which occurs RDATDLY bit clocks
earlier than the last transmitted bit of the previous frame. Any one of three cases
can occur:
Case 1: Unexpected FSR pulses with RFIG = 1. This case is discussed in
section 8.3.6.1 and shown in Figure 11–21. Here, receive frame sync
pulses are ignored and the reception continues.
Case 2: Normal serial port reception. There are three reasons for a receive
not to be in progress:
J
This FSR is the first after RRST = 1.
J
This FSR is the first after DRR has been read clearing an RFULL con-
dition.
J
The serial port is in the inter-packet intervals. The programmed data
delay (RDATDLY) for reception may start during these inter-packet in-
tervals for the first bit of the next element to be received. Thus, at maxi-
mum frame frequency, frame synchronization can still be received
RDATDLY bit clocks before the first bit of the associated element.
For this case, reception continues normally, because these are not unex-
pected frame sync pulses.
Case 3: Unexpected receive frame synchronization with RFIG = 0 (unex-
pected frame not ignored). This case was shown in Figure 11–20 for maxi-
mum packet frequency. Figure 11–27 shows this case during normal
operation of the serial port with time intervals between packets. Unex-
pected frame sync pulses are detected when they occur the value in
RDATDLY bit clocks before the last bit of the previous element is received
on DR. In both cases, RSYNCERR in the SPCR is set. RSYNCERR can
be cleared only by receiver reset or by writing a 0 to this bit in the SPCR.
If RINTM = 11b in the SPCR, RSYNCERR drives the receive interrupt
(RINT) to the CPU.
Note:
Note that the RSYNCERR bit in the SPCR is a read/write bit, so writing a 1
to it sets the error condition. Typically, writing a 0 is expected.
Data Transmission and Reception
Multichannel Buffered Serial Ports
11-43
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