Table of Contents
Advertisement
Internal Data Memory Organization
2.6.6
DMA Accesses to Internal Memory
2.6.7
Data Endianness
2-18
The DMA controller can accesss any portion of one block of internal data
memory while the CPU is simultaneously accessing any portion of another
block. If both the CPU and the DMA controller are accessing the same block,
and portions of both accesses are to the same 16-bit bank, the DMA operation
can take place first or last, depending on the CPU/DMA priority settings. You
can use Figure 3–3 to determine DMA versus CPU conflicts. Assume that one
axis represents the DMA access and the other represents the CPU access
from one CPU data port. Then, perform this analysis again for the other data
port. If both comparisons yield no conflict, then there is no CPU/DMA internal
memory conflict. If either comparison yields a conflict, then there is a CPU/
DMA internal memory conflict. In this case, the priority is resolved by the PRI
bit of the DMA channel as described in Chapter 4, TMS320C6211 Two-Level
Internal Memory . If the DMA channel is configured as higher priority than the
CPU (PRI = 1), any CPU accesses are postponed until the DMA accesses fin-
ish and the CPU incurs a 1-CPU-clock wait state. If both CPU ports and the
DMA access the same memory block, the number of wait states increases to
two. If the DMA has multiple consecutive requests to the block required by the
CPU, the CPU is held off until all DMA accesses to the necessary blocks finish.
In contrast, if the CPU has higher priority (PRI = 0), then the DMA access is
postponed until the both CPU data ports stop accessing that bank. In this con-
figuration, a DMA access request never causes a wait state.
Two standards for data ordering in byte-addressable microprocessors exist:
Little-endian ordering, in which bytes are ordered from right to left, the
most significant byte having the highest address
Big-endian ordering, in which bytes are ordered from left to right, the most
significant byte having the lowest address
Both the CPU and the DMA controller support a programmable endianness.
This endianness is selected by the LENDIAN pin on the device.
LENDIAN = 1 selects little endian, and LENDIAN big. Byte ordering within word
and half word data resident in memory is identical for little-endian and big-en-
dian data. Table 2–5 shows which bits of a data word in memory are loaded
into which bits of a destination register for all possible CPU data loads from big-
or little-endian data. The data in memory is assumed to be the same data that
is in the register results from the LDW instruction in the first row. Table 2–7 and
Table 2–8 show which bits of a register are stored in which bits of a destination
memory word for all possible CPU data stores from big- and little-endian data.
The data in the source register is assumed to be the same data that is in the
memory results from the STW instruction in the first row.
Advertisement
Chapters
Table of Contents
