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HPI Signal Descriptions
7.2.8
Address Strobe Input: HAS
7.2.9
Interrupt to Host: HINT
7.2.10 HPI Bus Access
7-12
HAS allows HCNTL[1:0], HR/W, and HHWIL to be removed earlier in an ac-
cess cycle, which allows more time to switch bus states from address to data
information. This feature facilitates interface to multiplexed address and data
buses. In this type of system, an address latch enable (ALE) signal is often pro-
vided and is normally the signal connected to HAS.
Hosts with a multiplexed address and data bus connect HAS to their ALE pin
or an equivalent pin. HHWIL, HCNTL[1:0], and HR/W are latched on the falling
edge of HAS. When used, HAS must precede the latest of HCS, HDS1, or
HDS2. Hosts with separate address and data buses can tie HAS high. In this
case, HHWIL, HCNTL[1:0], and HR/W are latched by the latest falling edge of
HDS1, HDS2, or HCS while HAS stays inactive (high).
HINT is the host interrupt output that is controlled by the HINT bit in the HPIC. This
bit is set to 0 when the chip is being reset. This signal is described in more detail
in section 7.3.4. Thus, the HINT pin is high at reset.
Figure 7–6 and Figure 7–8 show HPI access timing for cases in which HAS is
not used. Figure 7–7 and Figure 7–9 show HPI access timing for cases in which
HAS is used. HSTROBE represents the internally generated strobe described
in Figure 7–5. Control signals: HCNTL[1:0], HR/W, HHWIL, and HBE[1:0] are
typically driven by the host. HCNTL[1:0] and HR/W should have the same val-
ues for both halfword accesses. HHWIL is shown separately to indicate that it
must be low for the first halfword transfer and high for the second. If HAS is not
used (if it is tied high as shown in Figure 7–6), the falling edge of HSTROBE
latches these signals. If HAS is used as shown in Figure 7–7 and Figure 7–9,
the falling edge of HAS latches these values. In this case, the falling edge of
HAS must precede the falling edge of HSTROBE. On a read, data is valid at
some time after the falling edge of HSTROBE. If valid data is not already present
in the HPID, the data is set up at the falling edge of HRDY and held until the rising
edge of HSTROBE. On a write, the host must set up data and HBE[1:0] on the
rising edge of HSTROBE. The HPI provides 32-bit data to the CPU through a
16-bit external interface. This is accomplished by automatically combining two
successive halfword transfers.
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