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Multichannel Selection Operation
11.6.3.3 End-of-Subframe Interrupt
11.6.4 DX Enabler: DXENA
Figure 11–51. DX Timing for Multichannel Operation
CLKX
DX
11-78
At the end of every subframe (16 elements or less) boundary during multichan-
nel operation, the receive interrupt (RINT) or transmit interrupt (XINT) to the
CPU is generated if RINTM = 01b or XINTM = 01b in the SPCR, respectively.
This interrupt indicates that a new partition has been crossed. You can then
check the current partition and change the selection of subframes in the A and/
or B partitions if they do not point to the current subframe. These interrupts are
two CPU-clock high pulses. If RINTM = XINTM = 01b when (R/X)MCM = 0
(nonmultichannel operation), interrupts are not generated.
The DX enabler is only available for the 'C6211/C6711 device. The DXENA
field in the serial port control register (SPCR) controls the high impedance en-
able on the DX pin. When DXENA = 1, the McBSP enables extra delay for the
DX pin turn-on time. This feature is useful for McBSP multichannel operations,
such as in a time-division multiplexed (TDM) system. The McBSP supports up
to 128 channels in a multichannel operation. These channels can be driven by
different devices in a TDM data communication line, such as the T1/E1 line.
In any multichannel operation where multiple devices transmit over the same
DX line, you need to ensure that no two devices transmit data simultaneously,
which results in bus contention. Enough dead time should exist between the
transmission of the first data bit of the current device and the transmission of
the last data bit of the previous device. In other words, the last data bit of the
previous device needs to be disabled to a high impedance state before the
next device begins transmitting data to the same data line, as shown in
Figure 11–51.
Disable time
(processor 0)
Dead time
B0 (processor 0)
Extra delay
if DXENA = 1 (processor 1)
B7 (processor 1)
No extra delay
even with DXENA = 1
B6 (processor 1)
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