Texas Instruments TMS320C6201 Reference Manual page 112

Tms320c6000 series peripherals

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Address Generation

In the case of word transfers, these registers must contain values that are multi-

ples of 4 and thus aligned on a word address. In the case of halfword transfers,

the values must be multiples of 2 and thus aligned on a halfword address. If un-

aligned values are loaded, operation is undefined. There is no alignment restric-

tion for byte transfers. All accesses to program memory must be 32 bits in width.

Also, you must be aware of the endianness when trying to read a particular 8-bit

or 16-bit field within a 32-bit register. For example, in little endian mode, an ad-

dress ending in 00b selects the least significant byte, whereas 11b selects the

least significant byte in big-endian mode.

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