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Timer Counting
Timer Counting / Timer Clock Source Selection: CLKSRC
12.4 Timer Counting
12.5 Timer Clock Source Selection: CLKSRC
12-8
The timer counter runs at the CPU clock rate. However, counting is enabled
on the low-to-high transition of the timer count enable source. This transition
is detected by the edge detect circuit shown in Figure 12–1. Each time an ac-
tive transition is detected, one CPU-clock-wide clock enable pulse is gener-
ated. To the user, this makes the counter appear as if it were getting clocked
by the count enable source. Thus, this count enable source is referred to as
the timer input clock source.
Once the timer reaches a value equal to the value in the timer period register,
the timer is reset to 0 on the next CPU clock. Thus, the counter counts from
0 to N. Consider the case where the period is 2 and the CPU clock/4 is selected
as the timer clock source (CLKSRC = 1). Once started, the timer counts the
following sequence: 0, 0, 0, 0, 1, 1, 1, 1, 2, 0, 0, 0, 1, 1, 1, 1, 2, 0, 0, 0 . Note
that although the counter counts from 0 to 2, the period is 8 (2*4) CPU clock
cycles rather than 12 (3*4) CPU clock cycles. Thus, the countdown period is
the value of TIMER PERIOD, not TIMER PERIOD+1.
Low-to-high transitions (or high-to-low transitions if INVINP = 1) of the timer
input clock allow the timer counter to increment. Two sources are available to
drive the timer input clock:
The input value on the TINP pin, selected by CLKSRC = 0. This signal is
synchronized to prevent any metastability caused by asynchronous
external inputs. The value present on the TINP pin is reflected by DATIN.
The CPU clock/4, selected by CKSRC = 1.
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