Texas Instruments TMS320C6201 Reference Manual page 431

Table 14–2. Characteristics of the Power-Down Modes
Power-Down
Trigger Action
Mode
PD1 write logic 001001b
or 010001b to bits
15-10 of the CSR
PD2 write logic 011010b to
bits 15-10 of the CSR
PD3 write logic 11100b to
bits 15-10 of the CSR
Wake-up Method
internal interrupt,
external interrupt or
Reset
Reset only
Reset only
Triggering, Wake-Up, and Effects
Effect on Chip's Operation
CPU halted (except for the interrupt logic)
Output clock from PLL is halted, stopping
the internal clock structure from switching
and resulting in the entire chip being
halted. Signal terminal PD is driven high.
All register and internal RAM contents are
preserved. All signal terminals behave the
same way as during Reset.
Input clock to the PLL stops generating
clocks. Signal terminal PD is driven high.
All register and internal RAM contents are
preserved. All signal terminals behave the
same way as during Reset. Following re-
set, the PLL needs time to re-lock, just as
it does following power-up.
Power-Down Logic 14-5