Texas Instruments TMS320C6201 Reference Manual page 421

External Interrupt Signal Timing
13.2 External Interrupt Signal Timing
EXT_INT4–7, and NMI are dedicated external interrupt sources. In addition, the
FSR and FSX can be programmed to directly drive the RINT and XINT signals.
Because these signals are asynchronous, they are passed through two regis-
ters before being sent to either the DMA or CPU. Figure 13–1 shows the timing
of external interrupt signals using INT4 as an example. This diagram is similar
to the one in the CPU Reference Guide. However, this diagram also shows the
delays for the external interrupt through the two synchronization flip-flops. Note,
that this delay is two CPU clock (CLKOUT1) cycles. However, if the EXT_INT4
input transitions during the setup and hold time with respect to the CLKOUT1
rising edge, this delay could be as long as 3 CLKOUT1 cycles. Once synchro-
nized, an additional 3 CLKOUT1 cycle delay occurs before the related interrupt
flag (IF4) is set.
The earliest cycle that the interrupt can be scheduled is one CLKOUT1 cycle
after IF4 is set. This is indicated by the active internal interrupt acknowledge
(IACK) signal as shown in Figure 13–1. The interrupt can be postponed or in-
hibited if not properly enabled as described in other chapters of the CPU Refer-
ence Guide. In that case, IACK will be also be postponed. Along with IACK,
the CPU sets the INUM signal to indicate which interrupt was taken. Externally,
the IACK pin pulse is extended to two CLKOUT2 cycles wide and synchro-
nized to CLKOUT2. Also, the INUM pin signal frames this external IACK with
one CLKOUT2 cycle of setup and hold, for a width of 4 CLKOUT2 cycles. Note
that even though INUM and IACK in the diagram are not valid on a CLKOUT2
rising edge, the internal circuitry still catches the transition and produces the
desired waveforms on the IACK and INUM pins.
The NMI can interrupt a maskable interrupt's fetch packet (ISFP) just before
the interrupt reaches E1. In this case an IACK and INUM for the NMI is not seen
because the IACK and INUM corresponding to the maskable interrupt is on the
pins.
Interrupt Selector and External Interrupts 13-5