Texas Instruments TMS320C6201 Reference Manual page 101

5.4 Initiating a Block Transfer
5.4.1 DMA Autoinitialization
Each DMA channel can be started independently, either manually through
direct CPU access or automatically through autoinitialization. Each DMA
channel can be stopped or paused independently through direct CPU access.
The status of a DMA channel can be observed by reading the STATUS field in
the DMA channel's primary control register.
Manual start operation: To start DMA operation for a particular channel, once
the desired values are written to all other DMA control registers, the desired val-
ue should be written to the DMA control register with START = 01b. Writing this
value to a DMA channel that has already been started has no effect. Once
started, the value on STATUS is 01b.
Pause operation: Once started, a DMA channel can be paused by writing
START = 10b. When paused, the DMA channel completes any write transfers
whose read transfer requests have completed. Also, if the DMA channel has all
of the necessary read synchronizations, one additional element transfer is al-
lowed to finish. Once paused, the value on STATUS becomes 10b after the
DMA has completed all pending write transfers.
Stop operation: The DMA controller can be stopped by writing START = 00b.
Stop operation is identical to pause operation. Once a DMA transfer is com-
pleted, unless autoinitialization is enabled, the DMA channel returns to the
stopped state and STATUS becomes 00b after the DMA has completed all
pending write transfers.
The DMA controller can automatically reinitialize itself after completion of a block
transfer. Some of the DMA control registers can be preloaded for the next block
transfer through selected DMA global data registers. Using this capability, some
of the parameters of the DMA channel can be set well in advance of the next block
transfer. Autoinitialization allows:
Continuous operation: The CPU is given a long slack time during which it can
reconfigure the DMA controller for a subsequent transfer. Normally, the CPU
would have to reinitialize the DMA controller immediately after completion of the
last write transfer in the current block transfer and before the first read synchro-
nization for the next block transfer. With the reload registers, it can reinitialize
these values for the next block transfer anytime after the current block transfer
begins.
Direct Memory Access (DMA) Controller
Initiating a Block Transfer
5-13