Texas Instruments TMS320C6201 Reference Manual page 126

DMA Controller Structure / DMA Action Complete Pins / Emulation DMA Action Complete Pins
5.11.4 DMA Performance
5.12 DMA Action Complete Pins
5.13 Emulation
5-38
The DMA controller can perform element transfers with single-cycle
throughput if it accesses separate resources for the read transfer and write
transfer and both these resources have single-cycle throughput. An example
is an unsynchronized block transfer from single-cycle external SBSRAM to
internal data memory without any competition from any other channels or the
CPU. The DMA controller performance can be limited by:
The throughput and latency of the resources it requests
Waiting for read, write, or frame synchronization
Interruptions by higher priority channels
Contention with the CPU for resources
The DMA action complete pins (DMAC0–DMAC3) provide a method of feed-
back to external logic by generating an event for each channel. If it is specified
by the DMAC EN field in the DMA channel secondary control register, the DMAC
pin can reflect the status of RSYNC STAT, WSYNC STAT, BLOCK COND, or
FRAME COND or be treated as a high or low general purpose output. If the
DMAC pin reflects RSYNC STAT or WSYNC STAT externally, then once a syn-
chronization event has been recognized, DMAC transitions from low-to-high.
Once that event has been serviced as indicated by the status bit being cleared,
DMAC changes from high-to-low. Before being sent off chip, the DMAC signals
are synchronized by CLKOUT1. The active period of these signals is a minimum
of two CLKOUT1 periods wide.
When you are using the emulator for debugging, you can halt the CPU on an exe-
cute packet boundary for single-stepping, benchmarking, profiling, or other de-
bugging purposes. You can configure the DMA controller pause during this time
or to continue running. This configuration is accompanied by setting the EMOD
bit in the DMA primary control register to 0 or 1. If the DMA controller is paused,
the STATUS field reflects the paused state of the channel. The auxiliary channel
continues running during an emulation halt. This emulation closely simulates
single-stepping DMA transfers. DMA channels with EMOD = 1 can couple
multiple transfers between single steps; a successful step can require multiple
outstanding transfers to finish first.