Texas Instruments TMS320C6201 Reference Manual page 222

Expansion Bus Host Port Operation
8.5.2.1 TMS320C6202 Master on the Expansion Bus
8-28
When the 'C6202 is the master of the expansion bus, it can initiate a burst read
or write to a peripheral on the bus.
When the DSP controls the bus, data flow is controlled in a manner similar to
a DMA transfer; however, the expansion bus host channel controls the actual
data transfer. The event flow is as follows:
1) The DSP must initialize the XBEA, which dictates where in the external
slave memory map that data is accessed.
2) The XBIMA must be set to specify the source or destination address in the
DSP memory map where the transaction starts.
3) The XFRCNT field of the expansion bus host port control (XBHC) register
field is set to control the number of elements being transferred.
4) The start field is written,controlling whether the external access is a read
or write burst.
An interrupt is generated at the completion of the transfer if specified by the
INTSRC bit in the XBHC register.
Figure 8–19 and Figure 8–20 show examples of timing diagrams for a burst
read and write when the 'C6202 is mastering the bus. In this case internal bus
arbiter is disabled (XHOLD is output and XHOLDA is input) and 'C6202 wakes
up from reset as slave on the expansion bus.
The XWAIT signal prevents data overflow/underflow when the DSP is a master
on the expansion bus. The XWAIT signal, which is multiplexed with the XWE
signal, can be thought of as a ready output when the 'C6202 initiates transfers
on the expansion bus. By asserting the XWAIT signal low, the 'C6202 (the
'C6202 initiated a transaction) indicates that it is not ready to deliver/receive
new data.