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Expansion Bus Host Port Operation
Cycle Description
8-36
Each access initiated by the external host can be broken up into distinct cate-
gories:
Address phase (Ta): During the address phase, the 'C6x is selected with
the XCS input and the address phase is started with a low pulse on the
XAS signal. During this phase, the 'C6x determines if the external master
is doing a read or write cycle (XW/R input) and which expansion bus regis-
ter is being accessed (via the XCNTL input).
Wait/data phase (Tw/Td): Immediately after the address phase, the
transaction enters either the wait phase or data phase. For a read cycle,
there is at least one wait phase before the 'C6x presents the data to the
external host. This is controlled via the XRDY output of the 'C6x. If the
XRDY signal is high, this indicates to the external host that the 'C6x is not
ready to receive data for a write, or is not ready to present data for a read,
and is in the wait phase. The data phase is entered when the 'C6x asserts
XRDY signal, indicating that read data should be latched by the external
host or that write data has been latched by the 'C6x.
Recovery phase (Tr): The recovery phase is entered after final data
phase of a burst access or after the data phase of a single access. When
the 'C6x is a slave, if the external master has a multiplexed address/data
bus, it is recommended that the external master insert at least one recov-
ery phase between a read data phase and a subsequent address phase
in order to avoid potential bus contention.
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