Texas Instruments TMS320C6201 Reference Manual page 464

Index
EMIF to SRAM interface, figure 9-50
EMU0/1
configuration 15-19, 15-22
emulation pins 15-18
IN signals 15-18
rising edge modification 15-21
EMU0/1 signals 15-2, 15-5, 15-6, 15-11, 15-16
emulation
JTAG cable 15-1
timing calculations 15-6 to 15-7, 15-16 to 15-24
emulation halt 9-64
emulator
connection to target system, JTAG mechanical
dimensions 15-12 to 15-24
designing the JTAG cable 15-1
emulation pins 15-18
signal buffering 15-8 to 15-11
target cable, header design 15-2 to 15-3
emulator mode, direct memory access (DMA) 5-38
emulator pod, JTAG timings 15-5
enabling counting 12-7
endianness 6-27
data memory 2-18
direct memory access 5-23
enhanced data memory controller 9-6
enhanced direct memory access (EDMA) 1-7
enhanced DMA 4-2
enhanced DMA controller 4-2, 6-9
ER bit 6-7
error condition 6-7
ESIZE 6-14
ESIZE field 6-27
even N parameters 6-25
event
chaining EDMA channels 6-34
McBSP0 receive 6-18
McBSP0 transmit 6-18
Event Clear Register (ECR), figure 6-8
event clear register (ECR) 6-6
Event Enable Register (EER), figure 6-7
event enable register (EER) 6-6
event encoder 6-8, 6-17
event flags 5-18
Event Processing and EDMA Control
Registers 6-6
Event Register (ER), figure 6-7
Index-6
event register (ER) 6-6
Event Set Register (ESR), figure 6-8
event set register (ESR) 6-6, 6-7
event set register, ESR 6-17
event–triggered EDMA 6-17
events, synchronization 11-7
example, dual–phase frame 11-26
Example of the Expansion Bus Interface to Four
8–Bit FIFOs, figure 8-11
Example of the Expansion Bus Interface to Two
16–Bit FIFOs, figure 8-12
examples
DMA single frame transfer 8-20
DMA transfer 8-20
transfer with frame synchronization 8-21
two–dimensional block transfer with frame
sync 6-23
expansion bus 1-9, 8-1
'C6202 master 8-28
'C6202 slave on 8-35
arbitration 8-44
block diagram 8-2
boot configuration, pullup and pulldown
resistors 8-50
boot configuration control 8-49
data 8-7
data (XBD) register 8-7
data register 8-23
description 1-10
external address 8-7
external address (XBEA) register 8-6
external address register 8-24
global control register 8-8
global control register fields 8-8
host channel 8-2
host port control 8-7
host port interface control register 8-24
host port registers 8-23
I/O port operation 8-10
interface in the TMS320C6202, block
diagram 8-4
internal master address (XBIMA) register 8-6
internal master address register 8-7, 8-24
internal slave address 8-7
internal slave address (XBISA) register 8-7
internal slave address register 8-23
pin description
asynchronous host port mode 8-41
synchronous host port mode 8-26