Texas Instruments TMS320C6201 Reference Manual page 360

Data Transmission and Reception
Figure 11–24. Serial Port Receive Overrun
CLKR
FSR
DR
A1 A0 B7
RRDY
RBR–to–DRR copy (A)
RFULL
Figure 11–25. Serial Port Receive Overrun Avoided
CLKR
FSR
DR
A1 A0
RRDY
RBR–to–DRR copy (A)
RFULL
11-42
yet. Another element, C, arrives and fills RSR. DRR is finally read, but not earli-
er than two and one half cycles before the end of element C. New data D over-
writes the previous element C in RSR. If RFULL is still set after the DRR is read,
the next element can overwrite D if DRR is not read in time.
B6 B5 B4 B3 B2
No Read of DRR (A) No RBR–to–DRR copy (B)
Figure 11–25 shows the case in which RFULL is set but the overrun condition
is averted by reading the contents of DRR at least two and a half cycles before
the next element, C, is completely shifted into RSR. This ensures that a RBR-
to-DRR copy of data B occurs before the next element is transferred from RSR
to RBR.
B7 B6 B5 B4 B3
No Read of DRR (A)
B1 B0 C7 C6 C5
B2 B1 B0 C7 C6
No RBR–to–DRR copy (B)
C4 C3 C2 C1 C0
No RSR–to–RBR copy(C)
No Read of DRR(A)
C5 C4 C3 C2 C1
RBR–to–DRR (B)
Read of DRR (A)
D7
C0