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15.5 JTAG Emulator Cable Pod Signal Timing
Figure 15–3. JTAG Emulator Cable Pod Timings
Table 15–2. Emulator Cable Pod Timing Parameters
No.
Reference
1
t
c(TCK)
2
t
w(TCKH)
3
t
w(TCKL)
4
t
d(TMS)
5
t
su(TDO)
6
t
h(TDO)
Figure 15–3 shows the signal timings for the emulator cable pod. Table 15–2
defines the timing parameters. These timing parameters are calculated from
values specified in the standard data sheets for the emulator and cable pod
and are for reference only. Texas Instruments does not test or guarantee these
timings.
The emulator pod uses TCK_RET as its clock source for internal synchroni-
zation. TCK is provided as an optional target system test clock source.
TCK_RET
TMS/TDI
TDO
Description
TCK_RET period
TCK_RET high-pulse duration
TCK_RET low-pulse duration
Delay time, TMS/TDI valid from TCK_RET low
TDO setup time to TCK_RET high
TDO hold time from TCK_RET high
JTAG Emulator Cable Pod Signal Timing
1
2
3
4
5
Designing for JTAG Emulation
1.5 V
6
Min Max Units
35
200
ns
15
ns
15
ns
6
20
ns
3
ns
12
ns
15-5
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