Texas Instruments TMS320C6201 Reference Manual page 353

Tms320c6000 series peripherals
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Figure 11–18. Transmit Operation
CLKX
FSX
DX
A1
A0
XRDY
DXR to XSR copy
(B)
11.3.5.3 Maximum Frame Frequency
B7
B6
B5
The frame frequency is determined by the following equation, which calculates
the period between frame synchronization signals:
Frame frequency
Number of bit clocks between frame sync signals
The frame frequency may be increased by decreasing the time between frame
synchronization signals in bit clocks (which is limited only by the number of bits
per frame). As the frame transmit frequency is increased, the inactivity period
between the data frames for adjacent transfers decreases to 0. The minimum
time between frame synchronization pulses is the number of bits transferred per
frame. This time also defines the maximum frame frequency, which is calculated
by the following equation:
Maximum frame frequency
Figure 11–19 shows the McBSP operating at maximum frame frequency. The
data bits in consecutive frames are transmitted continuously with no inactivity
between bits. If there is a 1-bit data delay, as shown, the frame synchronization
pulse overlaps the last bit transmitted in the previous frame.
B4
B3
B2
B1
B0
Write of DXR
DXR to XSR copy
(C)
(C)
it clock frequency
it clock frequency
Number of bits per frame
Multichannel Buffered Serial Ports
Data Transmission and Reception
C7
C6
Write of DXR
C5
(D)
11-35

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