Texas Instruments TMS320C6201 Reference Manual page 221

Table 8–16. Expansion Bus Pin Description (Synchronous Host Port Mode) (Continued)
Signal Signal
Symbol Type
XD[31:0] I/O/Z
XBLAST I/O/Z
XAS I/O/Z
XCNTL I
XBE[3:0]/ I/O/Z
XA[5:2]
XW/R I/O/Z
XRDY I/O/Z
XBOFF I
XWAIT O
Signal Signal
Count Name
32 Address/
data bus
1 Burst last
1 Address
Strobe
1 Control
signal
4 Byte
enables
1 Read/write
1 Ready out
Ready in
1 Bus
Back-Off
1 Wait
Expansion Bus Host Port Operation
Signal Function
Data
Signal driven by the current expansion bus master to
indicate the last transfer in a bus access. Input polarity
selected at boot. Output polarity is always active low.
Indicates a valid address and the start of a new bus access.
Asserted for the first clock of a bus access.
This signal selects between XBD and XBISA register.
XCNTL=0: access is made to the XBD register
XCNTL=1: access is made to the XBISA register
During host-port accesses these signals operate as
XBE[3:0].
BE3 byte enable 3: XD[31:24]
BE2 byte enable 2: XD[23:16]
BE1 byte enable 1: XD[15:8]
BE0 byte enable 0: XD[7:0]
Write/read enable
Polarity of this signal is configured during boot.
Active(low) during host-port access. XRDY is an input when
the 'C6202 owns the bus. When the 'C6202 does not own
the bus, XRDY is not driven until a request is made to the
'C6202.
When asserted, suspends the current access and the
'C6202 releases ownership of the expansion bus.
Ready output for master accesses
Expansion Bus 8-27