Texas Instruments TMS320C6201 Reference Manual page 462

Index
data memory
access 2-8
alignment 2-15
DMA accesses to 2-18
dual CPU access of 2-15
endianness 2-18
organization 2-9
TMS320C6201 revision 2 2-9
TMS320C6201 revision 2, figure 2-10
TMS320C6201 revision 2, table 2-9
TMS320C6201 revision 3 2-11
TMS320C6201 revision 3, figure 2-12
TMS320C6201 revision 3, table 2-11
TMS320C6701 2-13
TMS320C6701, figure 2-14
TMS320C6701, table 2-13
data memory controller 1-6, 2-8, 9-5
data memory controller (DMEMC) 3-7
data packing 11-28, 11-39
data path A 3-7, 8-4
data path B 3-7
data RAM address mapping 3-7
data receive (DR) pin 11-4
data receive register (DRR) 11-4
data reception 11-18
data register 7-8
data register, HPID 7-8
data registers 1-11
data transfe 6-17
data transfer 6-6
data transmission 11-18
data transmit (DX) pin 11-4
data write access 7-8
deactivation, SDRAM 9-35
debugger, interface 1-5
decision tree response to receive frame sync pulse,
figure 11-44
default interrupt mapping 13-9
definitions, EDMA 6-5
delay, data 11-30
Destination / source (address) update mode 6-14
destination address 6-13
destination address registers 5-22
destination update mode (DUM) 6-31
determining ready status 11-21
device reset 10-2, 11-19
Index-4
diagnostic applications 15-23
diagram
expansion bus block 8-2
expansion bus host port interface block 8-22
expansion bus interface in the
TMS320C6202 8-4
expansion bus XCE (0/1/2/3) space control
register 8-9
host port interface block of TMS320C6211 7-5
internal memory block 4-3
L1D, 2–way set associative cache diagram 4-11
L1P, direct mapped cache 4-7
TMS320C6201/6202/C6701 1-9
TMS320C6201/C6701 1-10
TMS320C6202 data memory controller
block 3-7
TMS320C6202 program memory controller 3-3
TMS320C6211 block 4-2, 6-2, 7-3
digital loop back (DLB) 11-52
digital signal processors (DSPs) 1-1
digital subscriber loop (DSL) 1-4
dimensions
12-pin header 15-18
14-pin header 15-12
mechanical, 14-pin header 15-12
direct memory access 1-8
direct memory access (DMA) 1-6, 1-7, 1-9
action complete pins 5-38
address generation 5-22
autoinitialization 5-13
automated event clearing 5-19
synchronization 5-17
block transfers 5-13
channel condition 5-33
channel control registers 5-8
channel event flags 5-18
channel reload registers 5-14
emulator mode 5-38
endianness 5-23
FIFO 5-36
holding registers 5-37
memory map 5-12
overview 5-2
performance limits 5-38
priority configuration 5-30
registers 5-5
split channel operation 5-28
structure 5-35
transfer counting register 5-16