Texas Instruments TMS320C6201 Reference Manual page 90

Overview
5.1 Overview
5-2
The direct memory access (DMA) controller transfers data between regions
in the memory map without intervention by the CPU. The DMA controller al-
lows movement of data to and from internal memory, internal peripherals, or
external devices to occur in the background of CPU operation. The DMA con-
troller has four independent programmable channels, allowing four different
contexts for DMA operation. In addition, a fifth (auxiliary) channel allows the
DMA controller to service requests from the host port interface (HPI). In dis-
cussing DMA operations, several terms are important:
Read transfer: The DMA controller reads a data element from a source
location in memory.
Write transfer: The DMA controller writes the data element that was read
during a read transfer to its destination in memory.
Element transfer: This form refers to the combined read and write transfer
for a single data element.
Frame transfer: Each DMA channel has an independently programmable
number of elements per frame. In completing a frame transfer, the DMA
controller moves all elements in a single frame.
Block transfer: Each DMA channel also has an independently program-
mable number of frames per block. In completing a block transfer, the
DMA controller moves all frames that it has been programmed to move.
Transmit element transfer: In split mode, data elements are read from the
source address, and writing it to the split destination address. See section
5.8 for details.
Receive element transfer: In split mode, data elements are read from the
split source address, and writing it to the destination address. See section
5.8 for details.
The DMA controller has the following features:
Background operation: The DMA controller operates independently of the
CPU.
High throughput: Elements can be transferred at the CPU clock rate. See
section 5.11, Structure , on page 5-35 for more information.
Four channels: The DMA controller can keep track of the contexts of four
independent block transfers. See section 5.2, DMA Registers , on page
5-5 for more information about saving the contents of multiple block
transfers.