Texas Instruments TMS320C6201 Reference Manual page 86

4.5.3 L2 EDMA Service
4.5.4 L2 Invalidation
EDMA accesses are only allowed to L2 space that is configured as mapped
RAM. When the EDMA makes a read request to the L2, the L2 snoops the data
from the L1D and stalls the EDMA until a response is returned. If data that
must be updated is returned, that data is placed in the L2 and the EDMA re-
quest proceeds. In this case, the L1D line is invalidated to maintain coherency.
If the L1D does not return data to the L2 then the data is read from the L2. The
L2 does not snoop the L1P for data when a EDMA read request is received
because the CPU cannot modify data in L1P so it's data will not be incoherent.
When the EDMA makes a write request to the L2, both the L1P and the L1D
are snooped for the data. Both the L1P and the L1D must be notified of the
write because the L2 has no knowledge of the type of data being written by the
EDMA, whether program or data. If the L1P responds that it is caching the ad-
dressed data, then that line is invalidated and the data is written into L2. Simi-
larly, if the L1D is caching that address, then that line in the L1D is invalidated
and the data is written to L2. By invalidating the lines in the L1P or the L1D,
the correct data will be fetched from the L2 on the next CPU request of that
data.
The method for user controlled invalidation of data in the L2 is similar to those
for the L1P and the L1D. For the L2, however, there are two types of invalida-
tion. The first type of invalidation is an L2 flush. During a flush, the contents
of the L2 are copied out through the enhanced DMA. Like an EDMA read or
L2 data eviction, the L1D is snooped for any modified (dirty) data that is being
copied out by the flush. The second type of L2 invalidation is a clean. The
clean operation copies data from the L2 through the EDMA to the external
memory space and snoops data from the L1D. In addition, the clean operation
invalidates any line in the L1P, L1D, or L2 that caches data that is copied to the
external memory space.
To initiate an L2 flush of the entire L2 cache space, write a 1 to the F bit of the
L2FLUSH register. This bit remains set to 1 until the flush is complete at which
time the register is cleared to 0 by the L2 controller. Figure 4–16 shows the
fields of the L2FLUSH register. Table 4–8 describes the operation of the
L2FLUSH register. Similarly, to initiate an L2 clean of the entire L2 cache
space set the C bit of the L2CLEAN register to 1. This bit remains set to 1 until
the clean is complete at which time the register is cleared to 0. Figure 4–17
shows the fields of the L2CLEAN register. Table 4–9 describes the operation
of the L2CLEAN register.
TMS320C6211/C6711 Two-Level Internal Memory
L2 Description
4-21