Texas Instruments TMS320C6201 Reference Manual page 378

Tms320c6000 series peripherals
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Programmable Clock and Framing
11.5.2.5 Digital Loopback Mode: DLB
11.5.2.6 Receive Clock Selection: DLB, CLKRM
Table 11–15. Receive Clock Selection
DLB
CLKRM
in SPCR
in PCR
0
0
0
1
1
0
1
1
11-60
These figures show what happens to CLKG when it is initially in sync and
GSYNC = 1, as well as when it is not in sync with the frame synchronization
and GSYNC = 1.
When GSYNC = 1, the transmitter can operate synchronously with the receiv-
er, provided that the following conditions are met:
FSX is programmed to be driven by the sample rate generator frame sync,
FSG (FSGM = 1 in the SRGR and FSXM = 1 in the PCR). If the input FSR
has timing that enables it to be sampled by the falling edge of CLKG, it can
be used instead by setting FSXM = 0 in the PCR and connecting FSR to
FSX externally.
The sample-rate generator clock should drive the transmit and receive bit
clock (CLK(R/X)M = 1 in the SPCR). Therefore, the CLK(R/X) pin should
not be driven by any other source.
Setting DLB = 1 in the SPCR enables digital loopback mode. In DLB mode, DR,
FSR, and CLKR are internally connected through multiplexers to DX, FSX, and
CLKX, respectively, as shown in Figure 11–37. DLB mode allows testing of se-
rial port code with a single DSP device.
Table 11–15 shows how the digital loopback bit (DLB) and the CLKRM bit in
the PCR select the receiver clock. In digital loopback mode (DLB = 1), the
transmitter clock drives the receiver. CLKRM determines whether the CLKR
pin is an input or an output.
Source of Receive Clock
CLKR acts as an input driven by the
external clock and inverted as deter-
mined by CLKRP before being used.
The sample rate generator clock
(CLKG) drives CLKR.
CLKX_int drives the receive clock
CLKR_int as selected and is in-
verted. See Table 11–16.
CLKX_int drives CLKR_int as se-
lected
and
is
inverted.
Table 11–16.
CLKR Function
Input
Output. CLKG inverted as determined by
CLKRP before being driven out on CLKR.
High impedance
Output. CLKR (same as CLKX) inverted as
See
determined by CLKRP before being driven
out.

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