Texas Instruments TMS320C6201 Reference Manual page 334

McBSP Interface Signals and Registers
Table 11–7. Receive/Transmit Control Register (RCR/XCR) Field Descriptions (Continued)
Name Function
XWDLEN(1/2) Transmit element length in phase 1 and phase 2
XWDLEN(1/2) = 000b: 8 bits
XWDLEN(1/2) = 001b: 12 bits
XWDLEN(1/2) = 010b: 16 bits
XWDLEN(1/2) = 011b: 20 bits
XWDLEN(1/2) = 100b: 24 bits
XWDLEN(1/2) = 101b: 32 bits
XWDLEN(1/2) = 11Xb: Reserved
RCOMPAND Receive companding mode. Modes other than 00b are only applicable
when the appropriate RWDLEN is 000b, indicating 8-bit data.
RCOMPAND = 00b: No companding. Data transfer starts with MSB first.
RCOMPAND = 01b: No companding, 8-bit data. Transfer starts with LSB first.
RCOMPAND = 10b: Compand using µ-law for receive data.
RCOMPAND = 11b: Compand using A-law for receive data.
XCOMPAND Transmit companding mode. Modes other than 00b are only applicable when the
appropriate XWDLEN is 000b, indicating 8-bit data.
XCOMPAND = 00b: No companding, Data transfer starts with MSB first.
XCOMPAND = 01b: No companding, 8-bit data. Transfer starts with LSB first.
XCOMPAND = 10b: Compand using µ-law for transmit data.
XCOMPAND = 11b: Compand using A-law for transmit data.
RFIG Receive frame ignore
RFIG = 0:
RFIG = 1:
XFIG Transmit frame ignore
XFIG = 0: Unexpected transmit frame synchronization pulses restart the
XFIG = 1: Unexpected transmit frame synchronization pulses are ignored.
11-16
Unexpected receive frame synchronization pulses restart the
transfer.
Unexpected receive frame synchronization pulses are ignored.
transfer.
Section
11.3.4.5
11.4
11.4
11.3.6.1
11.3.6.1