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Quick DMA (QDMA)
sible to submit the first QDMA request in as little as five cycles (one cycle write
for each of the five QDMA registers), as opposed to 36 cycles for the first
EDMA transfer request (6-cycle store for each of the six EDMA transfer param-
eters). Therefore, the QDMA registers can be used within the context of tight
loop algorithms if desired.
Furthermore, the QDMA registers retain their value even after submitting the
DMA transfer request. Hence, all five of the registers need not be programmed
for each DMA submitted, provided that other application code has not modified
these registers since the last DMA transfer request. As a result, subsequent
QDMA requests can be processed in as little as one cycle per request-where
the user only modifies the ONE corresponding pseudo-mapping register.
6.16.5 QDMA Stalls and Priority
The QDMA has several stalling conditions. Once a write has been performed
to one of the pseudo-registers (resulting in a pending QDMA transfer request),
future writes to the QDMA registers are stalled until the transfer request is sent.
Normally this will occur for 2 cycles, as this is how long it takes to submit a
transfer. The L2 controller includes a four-entry write buffer, so that stalls are
not generally seen by the CPU.
Because the QDMA and the L2 cache controller share the same transfer re-
quest node, cache activity requiring the use of this transfer request node may
delay submission of the QDMA transfer request. The L2 controller is given
priority during this sort of arbitration, as in general it is assumed the cache re-
quests have a greater likelihood of eventually stalling the CPU. The L2 write
buffer typically keeps the CPU from being affected by this stall condition.
Similar to the EDMA channels, QDMA can have programmable priority in the
two lower levels as described in section 6.14. The PRI bit-field in the
QDMA_OPT register specifies the priority level of the QDMA. Once again, lev-
el 0 (urgent priority) is reserved for L2 cache accesses. QDMA request priority
needs to be set to either level 1 (PRI = 001b) or level 2 (PRI = 010b). QDMA
requests with any other level not equal to 1 or 2 will be discarded.
In the case when an EDMA request and a QDMA request happen simulta-
neously, the QDMA request will get submitted first. However, this only applies
to the order of request submission. The PRI field determines the actual priority
of the request. An EDMA request with level 1 priority has higher priority than
a QDMA request with level 2 priority, even if the two events happen simulta-
neously and the QDMA request gets submitted first. Therefore, it is very impor-
tant that the user programs the PRI field to specify the priority of an EDMA/
QDMA request, rather than relying on the order of the requests.
EDMA Controller
6-41
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