Timer Interrupts - Texas Instruments TMS320C6201 Reference Manual

12.7 Boundary Conditions in the Control Registers

12.8 Timer Interrupts

12.9 Emulation Operation
Boundary Conditions in the Control Registers / Timer Interrupts / Emulation Operation
The following boundary conditions affect timer operation:
1) Timer period and counter register value is 0: After device reset and before
the timer starts counting, TSTAT is held at 0. After the timer starts running
by setting HLD = 1 and GO = 1, while the period and counter registers are
zero, the operation of the timer depends on the C/P mode selected. In
pulse mode, the TSTAT = 1 regardless of whether or not the timer is held.
In clock mode, when the timer is held (HLD = 0), TSTAT keeps it's previous
value and when HLD = 1, TSTAT toggles with a frequency of 1/2 of the CPU
clock frequency.
2) Counter overflow: When the counter register is set to a value greater than
the value of the period register, the counter reaches its maximum value
(FFFF FFFFh), rolls over to 0, and continues.
3) Writing to registers of an active timer: Writes from the peripheral bus over-
ride register updates to the counter register and new status updates to the
control register.
4) Small timer period values in pulse mode: Note that small periods in pulse
mode can cause TSTAT to remain high. This condition occurs when TIMER
PERIOD PWID + 1.
The TSTAT signal directly drives the CPU interrupt as well as a DMA synchro-
nization event. The frequency of the interrupt is the same as the frequency of
TSTAT.
During debug using the emulator, the CPU may be halted on an execute packet
boundary for single stepping, benchmarking, profiling, or other debug uses.
During an emulation halt, the timer halts when the CPU clock/4 is selected as
the clock source (CLKSRC = 1). Here, the counter is only enabled to count dur-
ing those cycles when the CPU is not stalled due to the emulation halt. Thus,
counting will be re-enabled during single-step operation. If CLKSRC = 0, the
timer continues counting as programmed.
Boundary Conditions in the Control Registers
Timers 12-11