Texas Instruments TMS320C6201 Reference Manual page 410

Table 12–2. Timer Control Register Field Descriptions (Continued)
Bitfield Description
HLD Hold. Counter may be read or written regardless of HLD value.
HLD = 0: Counter is disabled and held in the current state.
HLD = 1: Counter is allowed to count.
C/P Clock/pulse mode
C/P = 0: Pulse mode. TSTAT is active one CPU clock after the timer reaches the timer
period. PWID determines when it goes inactive.
C/P = 1: Clock mode. TSTAT has a 50% duty cycle with each high and low period one
countdown period wide.
PWID Pulse width. Only used in pulse mode (C/P = 0).
PWID = 0: TSTAT goes inactive one timer input clock cycle after the timer counter value
equals the timer period value.
PWID = 1: TSTAT goes inactive two timer input clock cycles after the timer counter val-
ue equals the timer period value.
CLKSRC Timer input clock source
CLKSRC = 0: External clock source drives the TINP pin.
CLKSRC = 1: CPU clock/4.
INVINP TINP inverter control. Only affects operation if CLKSRC = 0.
INVINP = 0: Uninverted TINP drives timer.
INVINP = 1: Inverted TINP drives timer.
TSTAT Timer status. Value of timer output.
INVOUT TOUT inverter control. Used only if FUNC = 1.
INVOUT = 0: Uninverted TSTAT drives TOUT.
INVOUT = 1: Inverted TSTAT drives TOUT.
Timer Registers
Section
12.3
12.6
12.6
12.5
12.5
12.6
Timers 12-5