9.4 Sdram Interface; Tms320C6201/C6202/C6701 Emif Sdram Commands - Texas Instruments TMS320C6201 Reference Manual

SDRAM Interface

9.4 SDRAM Interface

Table 9–8. TMS320C6201/C6202/C6701 EMIF SDRAM Commands
9-20
The TMS320C6201/C6202/C6701 EMIF supports 2-bank, 16M-bit SDRAM
and 4 bank, 64M-bit SDRAM, providing an interface to high-speed and high-
density memory. The EMIF supports the SDRAM commands shown in
Table 9–8. The 16M-bit and 64M-bit SDRAM interfaces are shown in
Figure 9–14 and Figure 9–16, respectively. Table 9–9 lists all of the possible
SDRAM configurations available via the TMS320C6201/C6202/C6701 EMIF.
The TMS320C6211/C6711 EMIF allows programming of the addressing char-
acteristics of the SDRAM, including the number of column address bits (page
size), the row address bits (pages per bank), and banks (maximum number of
pages which can be opened). Using this information, the 'C6211/C6711 is able
to open up to four pages of SDRAM simultaneously. The pages can all be in a
single CE space, or distributed across multiple CE spaces. Table 9–10 summa-
rizes the pin connection and related signals specific to SDRAM operation.
Table 9–8 does not apply to the 'C6211/C6711 because page characteristics
are programmable. The 'C6211/C6711 can interface to any SDRAM that has
8 to 10 column address pins, 11 to 13 row address pins, and two or four banks.
Command Function
DCAB Deactivate all banks
†
DEAC Deactivate a single bank
ACTV Activates the selected bank and select the row
READ Inputs the starting column address and begins the read operation
WRT Inputs the starting column address and begins the write operation
MRS Mode register set, configures SDRAM mode register
REFR Autorefresh cycle with internal address
† TMS320C6211/C6711 only
†