Texas Instruments TMS320C6201 Reference Manual page 473

EMIF SDRAM timing 9-17
event 6-6
event clear 6-6, 6-8
event enable 6-6, 6-8
event processing 6-6
event set 6-6, 6-7, 6-8
expansion bus 8-6
data 8-23, 8-35
external address 8-24
host port interface control 8-24
internal slave address 8-23, 8-35
expansion bus external address 8-6
expansion bus FIFO control 8-6
expansion bus global control 8-6, 8-8
expansion bus host port 8-6, 8-7
expansion bus host port interface control 8-6
expansion bus internal master address 8-6,
8-24
external interrupt polarity register 13-7
flush word count 4-8
general purpose 1-5
host-port interface 7-16
HPI control 7-16
HPIC 7-19
internal memory control 4-5, 4-13
interrupt 13-7
interrupt multiplexer 13-8
L1D , flush base address 4-12
L1D flush base address 4-5
L1P, flush word count 4-8
L1P flush base address 4-5
L2 CE space allocation 4-18, 4-19, 4-20
L2 flush base address 4-5
L1D flush word count 4-5
L2 flush word count 4-5
McBSP interface 11-3
memory attribute 4-5
memory attribute register (MAR) 4-18
mode register set 9-28
multichannel buffered serial port 11-3
multichannel control register (MCR) 11-6
page information 9-27
pin control register (PCR) 11-6, 11-11
receive buffer register (RBR) 11-4
receive channel enable register (RCER) 11-6
receive control register (RCR) 11-14
receive shift register (RSR) 11-4
reload 5-25
sample rate generator register (SRGR) 11-6
serial port control register (SPCR) 11-6, 11-7
space control 8-9
timer 12-4
timer counter 12-6
timer period 12-6
transfer counter 5-16
transmit channel enable register (XCER) 11-6
transmit control register (XCR) 11-14
transmit shift register (XSR) 11-4
writing to EMIF 9-63
XCE space control 8-9
XCE1 space control 8-6
XCE2 space control register 8-6
relevant registers (single frame transfer) 8-20
reload field 6-28
reload parameters 6-16, 6-25
reloading element count 6-28
remote access servers (RAS) 1-4
reset 10-2
device 11-19
McBSP 11-19
memory access through HPI 7-27
sample rate generator 11-20
serial port 11-18
resetting the timer 12-7
resource arbitration 6-36
REVT0 6-18
REVT1 6-18
ROM
16-bit 9-53
modes 9-52
run/stop operation 15-8
RUNB, debugger command 15-18, 15-19, 15-20,
15-21, 15-22
RUNB_ENABLE, input 15-20
S
sample rate generator
clocking and framing 11-54, 11-57
reset procedure 11-56
register 11-55
sample rate generator reset 11-20
SBSRAM
interface 9-43
reads 9-45
write 9-47
scan path linkers
secondary JTAG scan chain to an SPL 15-15
Index
Index-15