Texas Instruments TMS320C6201 Reference Manual page 398

SPI Protocol: CLKSTP
11.7 SPI Protocol: CLKSTP
Figure 11–52. SPI Configuration: McBSP as the Master
11-80
A system conforming to this protocol has a master-slave configuration. The
SPI protocol is a 4-wire interface composed of serial data in (master in slave
out or MISO), serial data out (master out slave in or MOSI), shift clock (SCK),
and an active (low) slave enable (SS) signal. Communication between the mas-
ter and the slave is determined by the presence or absence of the master clock.
Data transfer is initiated by the detection of the master clock and is terminated
on absence of the master clock. The slave has to be enabled during this period
of transfer. When the McBSP is the master, the slave enable is derived from the
master transmit frame sync pulse, FSX. Example block diagrams of the
McBSP as a master and as a slave are shown in Figure 11–52 and
Figure 11–53, respectively.
McBSP master
SPI compliant
CLKX
SCK
DX
MOSI
DR
MISO
FSX
SS
slave