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6.5 Parameter RAM (PaRAM)
Unlike the existing 'C6201 DMA controller which is a register-based architec-
ture, the enhanced DMA controller is a RAM-based architecture. The parame-
ter RAM as the name indicates is used to store the parameters that define a
particular EDMA transfer. The 2K byte parameter RAM holds transfer parame-
ters (or entries) for all the 16 events. Parameter entries can also be linked to
one another to provide for processing of complex streams, circular buffering,
and sorting functions. The link entries are also specified in the parameter RAM.
Once an event is captured, its parameters are read from one of the top 16 en-
tries in the PaRAM as shown in Table 6–2. These parameters are then sent
to the address generation hardware.
The contents of the 2K byte parameter RAM shown in Table 6–2 comprises:
16 transfer parameter entries for the 16 EDMA events. Each entry is six
words or 24 bytes totaling 384 bytes. Address range is 01A0 0000h to
01A0 017Fh.
69 transfer parameter sets that can be used for linking events. Each set
or entry is 24 bytes totaling 1656 bytes. Address range is 01A0 0180h to
01A0 07F7h.
8 bytes of unused RAM that can be used as scratch pad area. Address
range is 01A0 07F8h to 01A0 07FFh. Note that a part or entire EDMA RAM
can be used as a scratch pad RAM provided this area corresponding to
an event(s) is disabled. It is the user's responsibility to provide the transfer
parameters when the event is eventually enabled.
Parameter RAM (PaRAM)
EDMA Controller
6-9
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