Texas Instruments TMS320C6201 Reference Manual page 166

Quick DMA (QDMA)
6.16.2 QDMA Register Access
6.16.3 Pseudo Mappings
QDMA_SRC = SOME_SRC_ADDRESS;
QDMA_DST = SOME_DST_ADDRESS;
QDMA_CNT = LINE_CNT<<16 | NUM_ELEMENTS & 0xFFFF;// Array Frame Count
QDMA_IDX = 0x00000000;
QDMA_S_OPT = 0x21B80001;
6.16.4 QDMA Performance
6-40
TCC field can have values between 0000b to 1111b, just as the TCC field in
the EDMA options parameter. Please refer to section 6.13 for detail. Similar
to the EDMA, the QDMA completion event is captured in the EDMA channel
interrupt pending register (CIPR). If the corresponding interrupt bit (specified
by the TCC field) in the EDMA channel interrupt enable register (CIER) is set,
the QDMA completion event will generate an interrupt to the CPU via the
EDMA interrupt signal, EDMA_INT. If you specify a TCC value in the
QDMA_OPT register to be between 8 and 11, chaining of the QDMA transfer
to an EDMA channel transfer is possible, provided the relevant bit in the chan-
nel chain enable register (CCER) is set. Refer to section 6.16.3 for detail.
Each of the QDMA registers is considered write only. Reads of the QDMA reg-
isters will return invalid data. Access to each of the above registers is limited
to 32-bits only. Halfword and byte writes to the QDMA registers will write the
entire register, and thus should be avoided.
The five physical QDMA registers are shadowed by five pseudo-mappings of
the same registers. The pseudo-mappings serve as the mechanism for actual-
ly submitting the transfer request for DMA service. Writes to the physical
QDMA registers (i.e. addresses 0200 0000h – 0200 0010h) are performed as
normal store operations. A write to any one of the pseudo-registers will per-
form a write to the corresponding physical register, and also submit a transfer
request for DMA service using the values stored in the physical registers.
Thus, a typical submission sequence might look like the following:
The QDMA mechanism is extremely efficient at submitting DMA requests.
Stores to the QDMA registers are passed to L2 cache as regular writes rather
than peripheral writes. Because the QDMA registers are decoded to a special
address region (0200 xxxxh), a fast decode is performed and writes may pro-
ceed to the QDMA registers on every cycle. Consequently, it is physically pos-
// no indexing specified
// frame synchronized 1D–SRC to 2D-DST,send
// completion code 8 when finished
// and submit transfer