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µ -LAW/A-LAW Companding Hardware Operation
m-LAW/A-LAW Companding Hardware Operation
Figure 11–36. Companding of Internal Data
RSR
DR
(DLB)
DX
11.4.1.1 Bit Ordering
11-52
Figure 11–36 shows two methods by which the McBSP can compand internal
data. Data paths for these two methods are indicated by (DLB) and (non-DLB)
arrows.
Non-DLB: When both the transmit and receive sections of the serial port
are reset, the DRR and DXR are internally connected through the com-
panding logic. Values from the DXR are compressed as determined by
XCOMPAND and then expanded as determined by RCOMPAND. RRDY
and XRDY bits are not set. However, data is available in DRR four CPU
clocks after being written to DXR. The advantage of this method is its
speed. The disadvantage is that there is no synchronization available to
the CPU and the DMA controller to control the flow of data.
DLB: The McBSP is enabled in digital loopback (DLB) mode with compand-
ing appropriately enabled by RCOMPAND and XCOMPAND. Receive and
transmit interrupts (RINT when RINTM = 0 and XINT when XINTM = 0) or
synchronization events (REVT and XEVT) allow synchronization of the CPU
or the DMA controller to these conversions, respectively. Here, the time for
this companding depends on the serial bit rate selected.
RBR
Expand
(non-DLB)
XSR
Compress
Normally, all transfers on the McBSP are sent and received with the MSB first.
However, certain 8-bit data protocols (that do not use companded data) require
the LSB to be transferred first. By setting the (R/X)COMPAND = 01b in the
(R/X)CR, the bit ordering of 8-bit elements is reversed (LSB first) before being
sent to the serial port. Like the companding feature, this feature is enabled only
if the appropriate (R/X)WDLEN(1/2) bit is set to 0, indicating that 8-bit elements
are to be transferred serially.
RJUST
DRR
DXR
From CPU/DMA controller
To CPU/DMA
controller
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