Texas Instruments TMS320C6201 Reference Manual page 383

11.5.4 Clocking Examples
11.5.4.1 Double-Rate ST-BUS Clock
Figure 11–43. ST-BUS and MVIP Example
4.096-MHz CLKS
FSR external
FSG, FSR_int,
FSX_int
2.048-MHz CLKG,
CLKR_int,
CLKX_int (first FSR)
DR, DX (first FSR)
CLKG, CLKR_int,
CLKX_int
(subsequent FSR)
DR, DX
(subsequent FSR)
Figure 11–43 shows the McBSP timing to be compatible with the Mitel ST-
Bus . The operation is running at maximum frame frequency.
CLK(R/X)M = 1: CLK(R/X)_int generated internally by sample rate generator
GSYNC = 1: CLKG is synchronized with the external frame sync signal in-
put on FSR. CLKG is not synchronized (it runs freely) until the frame sync
signal is active. Also, FSR is regenerated internally to form a minimum
pulse width.
CLKSM = 0: external clock (CLKS) drives the sample rate generator
CLKSP = 1: falling edge of CLKS generates CLKG and thus CLK(R/X)_int
CLKGDV = 1: receive clock (shown as CLKR) is half of CLKS frequency
FS(R/X)P = 1: active (low) frame sync pulse
(R/X)FRLEN1 = 11111b: 32 elements per frame
(R/X)WDLEN1 = 0: 8-bit element
(R/X)PHASE = 0: single-phase frame and thus (R/X)FRLEN2 =
(R/X)WDLEN2 = X
(R/X)DATDLY = 0: no data delay
Sample point
E1B7 E1B6
E32B0 E1B7 E1B6
E1B5 E1B4 E1B3
E1B5 E1B4
E1B3
Multichannel Buffered Serial Ports
Programmable Clock and Framing
E1B2 E1B1 E1B0
E1B2 E1B1 E1B0
E2B7
E2B7
11-65