Texas Instruments TMS320C6201 Reference Manual page 342

Data Transmission and Reception
11-24
Figure 11–37 on page 11-53). The receive data arriving at the DR pin is also
sampled on the falling edge of CLKR_int. These internal clock signals are either
derived from external source via the CLK(R/X) pins or driven by the sample rate
generator clock (CLKG) internal to the McBSP.
When FSR and FSX are outputs driven by the sample rate generator, they are
generated (transition to their active state) on the rising edge of the internal
clock, CLK(R/X)_int. Similarly, data on DX is output on the rising edge of
CLKX_int. See section 11.3.4.7 for more information.
FSRP, FSXP, CLKRP, and CLKXP configure the polarities of FSR, FSX, CLKR,
and CLKX, as indicated in Table 11–6. All frame sync signals (FSR_int and
FSX_int) internal to the serial port are active high. If the serial port is configured
for external frame synchronization (FSR/FSX are inputs to the McBSP) and
FSRP = FSXP = 1, the external active (low) frame sync signals are inverted be-
fore being sent to the receiver signal (FSR_int) and transmitter signal (FSX_int).
Similarly, if internal synchronization is selected (FSR/FSX are outputs and
GSYNC = 0), the internal active (high) sync signals are inverted if the polarity bit
FS(R/X)P = 1, before being sent to the FS(R/X) pin. Figure 11–37 shows this in-
version using XOR gates.
On the transmit side, the transmit clock polarity bit, CLKXP, sets the edge used
to shift and clock out transmit data. Data is always transmitted on the rising
edge of CLKX_int. If CLKXP = 1 and external clocking is selected (CLKXM =
0 and CLKX is an input), the external falling-edge-triggered input clock on
CLKX is inverted to a rising-edge-triggered clock before being sent to the
transmitter. If CLKXP = 1 and internal clocking is selected (CLKXM = 1 and
CLKX is an output pin), the internal (rising-edge-triggered) clock, CLKX_int,
is inverted before being sent out on the CLKX pin.
Similarly, the receiver can reliably sample data that is clocked (by the transmit-
ter) with a rising-edge clock. The receive clock polarity bit, CLKRP, sets the
edge used to sample received data. The receive data is always sampled on
the falling edge of CLKR_int. Therefore, if CLKRP = 1 and external clocking
is selected (CLKRM = 0 and CLKR is an input pin), the external rising-edge
triggered input clock on CLKR is inverted to a falling-edge clock before being
sent to the receiver. If CLKRP = 1 and internal clocking is selected (CLKRM
= 1), the internal falling-edge-triggered clock is inverted to a rising edge before
being sent out on the CLKR pin.