Pin Control Register (Pcr) - Texas Instruments AM1808 Technical Reference Manual

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Table 25-33. Use of the Transmit Channel Enable Registers (continued)
Number of
selectable channels

25.3.10 Pin Control Register (PCR)

The serial port is configured via the serial port control register (SPCR) and the pin control register (PCR).
The PCR contains McBSP status control bits. The PCR is shown in
Table 25-34.
31
15 14
Reserved
R-0
7 6
(1)
SCLKME Reserved
R/W-0 R-0
LEGEND: R = Read only; R/W = Rear/Write; -n = value afer reset
(1)
If writing to this field, always write the default value of 0 to ensure proper McBSP operation.
Bit Field Value
31-14 Reserved
13-12 Reserved
11 FSXM
10 FSRM
9 CLKXM
SPRUH82C – April 2013 – Revised September 2016
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Block Assignments
XCEREn Block assigned
XCERE3
Figure 25-51. Pin Control Register (PCR)
13 12
(1)
Reserved Reserved
R/W-0 R/W-0
5 4
Reserved Reserved
R/W-0 R-0
Table 25-34. Pin Control Register (PCR) Field Descriptions
Description
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
0 Reserved. The reserved bit location is always read as 0. A value written to this field has no effect. If
writing to this field, always write the default value of 0 to ensure proper McBSP operation.
Transmit frame-synchronization mode bit.
0 Frame-synchronization signal is derived from an external source.
1 Frame-synchronization signal is determined by FSGM bit in SRGR.
Receive frame-synchronization mode bit.
0 Frame-synchronization signal is derived from an external source. FSR is an input pin.
1 Frame-synchronization signal is generated internally by the sample-rate generator. FSR is an output
pin.
Transmit clock mode bit. When CLKSTP bit in SPCR is cleared to 0:
0 CLKX is an input pin and is driven by an external clock.
1 CLKX is an output pin and is driven by the internal sample-rate generator.
Copyright © 2013–2016, Texas Instruments Incorporated
(1)
XCEREn
Block 6
Block 7
Figure 25-51
Reserved
R-0
11 10
(1)
FSXM FSRM
R/W-0 R/W-0
3 2
FSXP FSRP
R/W-0 R/W-0
Multichannel Buffered Serial Port (McBSP)
Channel Assignments
Bit in
Channel assigned
XCE0 Channel 96
... ...
XCE15 Channel 111
XCE16 Channel 112
... ...
XCE31 Channel 127
and described in
9
CLKXM
R/W-0
1
CLKXP
R/W-0
Registers
(1)
16
8
CLKRM
R/W-0
0
CLKRP
R/W-0
1259