Texas Instruments TMS320C6201 Reference Manual page 374

Programmable Clock and Framing
Table 11–14. Sample Rate Generator Register (SRGR) Field Summary (Continued)
Name Function
FPER Frame period. This field's value plus 1 determines when the next frame sync signal
should become active.
Valid values: 0 to 4095
FWID Frame width. This field's value plus 1 is the width of the frame sync pulse, FSG,
during its active period.
Valid values: 0 to 255
CLKGDV Sample rate generator clock divider. This value is used as the divide-down number
to generate the required sample rate generator clock frequency. The default value
is 1. Valid values: 0 to 255
11.5.1.2 Sample Rate Generator Reset Procedure
11-56
The sample rate generator reset and initialization procedure is as follows:
1) During device reset, GRST = 0. Otherwise, during normal operation, reset
the sample rate generator with GRST = 0 in SPCR, provided CLKG and/or
FSG (FRST = 1) are not used by any portion of the McBSP. If GRST is low
due to device reset, CLKG is driven by a divide-by-2 internal clock and
FSG is driven inactive. The internal clock source for the 'C6211/C6711 is
CPU clock, while the internal clock source for 'C6211/C6711 is CPU/2
clock (half of the CPU clock frequency). CLKG and FSG are inactive when
GRST = 0. If necessary, set (R/X)RST = 0.
2) Program SRGR as required. If necessary, other control registers can be
written with desired values if the respective portion (R/X) is in reset.
3) Wait two CLKSRG clocks. This is to ensure proper internal synchronization.
4) Set GRST = 1 to enable the sample rate generator.
5) Wait two CLKG bit clocks.
6) Pull the receiver and/or transmitter out of reset ((R/X)RST = 1) if required.
7) On the next rising edge of CLKSRG, CLKG transitions to 1 and starts
clocking with a frequency equal to either (internal clock / (1+CLKGDV)) if
CLKSM =1 or CLKS clock/(1 + CLKGDV) if CLKSM = 0. The internal clock
source for the 'C6211/C6711 is CPU clock, while the internal clock source
for 'C6211/C6711 is CPU/2 clock (half of the CPU clock frequency).
8) After the required data acquisition setup, such as writing to DXR, FRST
can be written with 1 in the SPCR if an internally generated frame pulse is
required. FSG is generated on an active edge after eight CLKG clocks
have elapsed.
Section
11.5.3.1
11.5.3.1
11.5.2.2