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Emulation Design Considerations
15.9.2 Emulation Timing Calculations for SPL
15-16
The following examples help you to calculate the emulation timings in the SPL
secondary scan path of your system. For actual target timing parameters, see
the appropriate device data sheets.
Assumptions:
t
su(TTMS)
t
d(TTDO)
t
d(bufmax)
t
d(bufmin)
t
(bufskew)
t
(TCKfactor)
Given in the SPL data sheet:
t
d(DTMSmax)
t
su(DTDLmin)
t
d(DTCKHmin)
t
d(DTCKLmax)
There are two key timing paths to consider in the emulation design:
The TCK-to-DTMS/DTDO path, called t
The TCK-to-DTDI path, called t
Target TMS/TDI setup to TCK high
Target TDO delay from TCK low
Target buffer delay, maximum
Target buffer delay, minimum
Target buffer skew between two devices
in the same package:
[t
– t
d(bufmax)
d(bufmin)
Assume a 40/60 duty cycle clock
SPL DTMS/DTDO delay from TCK
low, maximum
DTDI setup time to SPL TCK
high, minimum
SPL DTCK delay from TCK
high, minimum
SPL DTCK delay from TCK
low, maximum
pd(TCK–DTDI)
]
0.15
, and
pd(TCK–DTMS)
.
10 ns
15 ns
10 ns
1 ns
1.35 ns
0.4
(40%)
31 ns
7 ns
2 ns
16 ns
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