Texas Instruments TMS320C6201 Reference Manual page 471

Tms320c6000 series peripherals
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XDATDLY 11-30
XSYNCERR 11-47
multichannel buffered serial ports (McBSPs) 1-8
multiphase frame example 11-32
multiplexed address 8-3
multiplexed device control 9-6
multiplier 1-5
multivendor interface protocol 1-11
MVIP networking standards 1-11
N
non–2–dimensional (non–2D) 6-20
non–2D EDMA transfer 6-21
Non–2D EDMA Transfer With Frame Sync,
figure 6-22
Non–2D R/W Sync EDMA Transfer Without Frame
Sync, figure 6-21
non–2D transfer, definition 6-5
O
off–chip memory 9-1
off–chip peripherals 8-1
on–chip data memory controller 9-2
on–chip peripherals 1-6, 1-7, 1-8, 7-2
on–chip program memory controller 9-2
on-chip peripherals, TDM serial port 11-78
operation
bootload 3-6
cache 3-5
DMA 5-13
I/O port 8-10
L2 4-15
McBSP standard 11-33
memory mapped 3-4
operation
receive 11-34
transmit 11-34
Options Bit–Fields, figure 6-13
options parameter in the EDMA channel/event
entry 6-13
order of processing 6-8
output strobes 8-3
overview, TMS320 family 1-2
P
Packing and unpacking 9-14
page boundaries, monitoring 9-25
PAL 15-19, 15-20, 15-22
parameter entry of an EDMA event 6-12
Parameter RAM 6-10, 6-11
parameter RAM 6-24, 6-36
parameter RAM (PaRAM) 6-9
parameter reload space in EDMA parameter
RAM 6-21
Parameter Storage for an EDMA Event,
figure 6-12
parameters of the expansion bus 8-8
pause operation 5-13
PCC field 3-4
PCI bridge chips 8-2
PCI interface chips 8-1
performance 6-37
peripheral bus 1-8, 2-21
byte and halfword access 2-21
causing CPU wait states 2-22
CPU/DMA arbitration 2-22
peripheral bus controller 3-7
peripheral registers 6-36
peripherals 1-8
phases, frame synchronization 11-25
pin control register (PCR), figure 11-11
pins, asynchronous interface 9-49
polarity register 13-7
power down 9-64
power down logic 8-4
Power–down logic 1-8
power-down logic 14-1
overview 14-2
PRWD field 14-3
triggering 14-4
wake-up selection 14-3
Power-down logic 10-1, 13-2
powerdown logic 4-2
PRI 6-14
Priority levels for EDMA events 6-14
priority processing 6-36
Priorty Queue Register (PQSR), figure 6-37
processing of events 6-6
Index
Index-13

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