Texas Instruments TMS320C6201 Reference Manual page 381

Table 11–17. Receive Frame Synchronization Selection
DLB FSR
in SPCR in PCR
0 0
0 1
0 1
1 0
1 X
1 1
11.5.3.3 Transmit Frame Sync Signal Selection: FSXM, FSGM
GSYNC Source of Receive Frame
in SRGR Synchronization
X External frame sync signal drives
the FSR input pin, whose signal is
then inverted as determined by
FSRP before being used as
FSR_int.
0 Sample rate generator frame
sync signal
FSR_int, FRST = 1.
1 Sample rate generator frame
sync signal
FSR_int, FRST = 1.
0 FSX_int drives FSR_int. FSX is
selected as shown in Table 11–18.
1 FSX_int drives FSR_int and is
selected as shown in Table 11–18.
0 FSX_int drives FSR_int and is
selected as shown in Table 11–18.
Table 11–18 shows how you can select the source of transmit frame synchro-
nization pulses. The three choices are:
External frame sync input
The sample rate generator frame sync signal, FSG
A signal that indicates a DXR-to-XSR copy has been made
Programmable Clock and Framing
FSR Pin Function
Input
Output. FSG is inverted as deter-
(FSG) drives mined by FSRP before being
driven out on the FSR pin.
Input. The external frame sync
(FSG) drives input on FSR is used to synchro-
nize CLKG and generate FSG.
High impedance
Input. External FSR is not used for
frame synchronization but is used
to synchronize CLKG and gener-
ate FSG since GSYNC = 1.
Output. Receive (same as transmit)
frame synchronization is inverted
as determined by FSRP before be-
ing driven out.
Multichannel Buffered Serial Ports 11-63