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9.9 Boundary Conditions When Writing to EMIF Registers
The EMIF has internal registers that change memory type, asynchronous
memory timing, SDRAM refresh, SDRAM initialization (MRS COMMAND),
clock speed, arbitration type, HOLD/NOHOLD condition, etc.
The following actions can cause improper data reads or writes:
Writing to the CE0, CE1, CE2, or CE3 space control registers
while an external access to that CE space is active
Changing the memory type (MTYPE) in the CE space control register
while any external operation is in progress (SDRAM type while
SDRAM initialization is active)
Changing the state of NOHOLD in the configuration while HOLD is active
at the pin
Changing the RBTR8 in the EMIF global control register while multiple
EMIF requests are pending
Initiating an SDRAM INIT (MRS) while the HOLD input or the HOLDA out-
put is active
J
The EMIF global control register can be read before the SDRAM INIT
bit is set to determine if the HOLD function is active, and it must
be read immediately after the SDRAM INIT bit is written to make sure
that the two events did not occur simultaneously.
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The EMIF global control register has status on the HOLD/HOLDA,
DMC/PMC/DMA active access and false access detection.
Boundary Conditions When Writing to EMIF Registers
External Memory Interface
9-63
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