Texas Instruments TMS320C6201 Reference Manual page 466

Index
clean register 4-22
clock rate 9-11
expansion bus arbiter 8-50
external master to DSP interrupt 8-25
FIFO clock enable (XFCEN) 8-8
FIFO mode 8-50
FIFO mode set by boot mode selection
(FMOD) 8-8
flush register 4-22
frame synchronization (FS) 6-13
host mode 8-50
internal memory control register 4-13
interrupt source 8-25
L1D
flush base address register 4-12
flush word count register 4-12
L1P
flush base address register 4-8
flush word count register 4-8
L2 CE space allocation register 4-18, 4-19,
4-20
L2 flush base address register 4-22
L2 flush register 4-22
L2 flush word count registers 4-23
LINK 6-13
little endian mode 8-50
memory map 9-11
memory type 8-9
MTYPE 9-13
polarity of expansion bus read/write signal 8-50
polarity of the XBLAST signal 8-50
program cache control 4-6
RBTR8 9-11
SBSRAM clock 9-10
SSCEN 9-10
start bus master transaction 8-25
TCC 6-13
TCINT 6-13
transfer counter 8-25
XBHC register 8-25
FIFO clock rate (XFRAT) 8-8
field description, timer control register 12-4
field descriptions 5-8
DMA channel secondary control register 5-10
pin control register 11-11
receive/transmit control registers 11-15
SPCR 11-8
fields, L2 flush register 4-22
FIFO control register 8-6
Index-8
FIFO Read Mode – Read Timing (glue–less case),
figure 8-17
FIFO Read Mode – With Glue, figure 8-18
FIFO Write Cycles, figure 8-16
first level memory 4-1
flag monitoring 8-19
flags, event 5-18
flow chart, L2 cache data request 4-17
flush and clean a range of addresses 4-22
flush base address register 4-5
flush base address register fields 4-8
flush begins when the L2FWC is written 4-22
flush word count register 4-5
format for the CCFG register 4-7, 4-13
frame, definition 6-5
frame (block) synchronization 6-19
frame count 5-16, 6-25
frame count (FC) 6-28
frame example, figure 11-26
frame frequency 11-35
frame index 6-25, 8-10
frame index (FIX) 6-20, 6-21, 6-24, 6-28
frame sync signal generation 11-61
frame period (FPER) 11-62
frame width (FWID) 11-62
FSGM 11-63
FSRM 11-62
FSXM 11-63
GSYNC 11-62
receive frame sync selection 11-62
transmit frame sync signal selection 11-63
frame synchronization 6-21
frame synchronization (FS) , field 6-13
frame synchronization ignore 11-36
frame synchronization phases 11-25
framesynchronization signal (FSR) 11-34
Frame Synchronized 2–D Transfer, figure 6-23
frame synchronized non–2D transfer 6-21
frame–synchronization signal generation 11-4
frame/array count, FC 6-5
Frame/Line Count 6-15
frames 6-5
freeze or bypass modes 4-6
function, L2 ALLOC bit 4-20