Texas Instruments TMS320C6201 Reference Manual page 125

DMA Controller Structure
a resource and the DMA controller controls the rate of consecutive requests and
the latency of received read transfer data.
The other function of the DMA FIFO is capturing read data from any pending
requests for a particular resource. For example, consider the situation in which
the DMA controller is reading data from pipelined external memory such as
SDRAM or SBSRAM into internal data memory. Assume that the CPU is given
higher priority over the DMA channel making requests and that it makes a com-
peting program fetch request to the EMIF. Assume that simultaneously the
CPU is accessing all banks of internal memory, blocking out the DMA controller.
In this case, the FIFO allows the pending DMAs to finish and the program fetch
to proceed. Due to the pipelined request structure of the DMA controller, at any
time the DMA controller can have pending read transfer requests whose data has
not yet arrived. Once enough requests to fill the empty spots in the FIFO are out-
standing, the DMA controller stops making further read transfer requests.
5.11.3 Internal Holding Registers
Each channel has dedicated internal holding registers. If a DMA channel is
transferring data through its holding registers rather than the internal FIFO,
read transfers are issued consecutively. Depending on whether the DMA con-
troller is in split mode or not, additional restrictions can apply:
In split mode, the two registers serve as separate transmit and receive data
stream holding registers for split mode. For both the transmit and receive read
transfer, no subsequent read transfer request is issued until the associated
write transfer request completes.
In nonsplit mode, once the data arrives a subsequent read transfer can be is-
sued without waiting for the associated write transfer to finish. However, be-
cause there are two holding registers, read transfers can get only one transfer
ahead of write transfers.
Direct Memory Access (DMA) Controller 5-37