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DMA Controller Structure
5.11.2 DMA FIFO
5-36
A 9-level DMA FIFO holding path facilitates bursting to high-performance memo-
ries, such as internal program and data memory, as well as external synchronous
DRAM (SDRAM) or synchronous burst SRAM (SBSRAM). When combined with
a channel's holding registers this path effectively becomes an 11-level FIFO. Only
one channel controls the FIFO at any given time. For a channel to gain control
of the FIFO, all of the following conditions must be met:
The channel does not have read or write synchronization enabled. Since
split-channel mode requires read and write synchronization, the FIFO is
not used by a channel in that mode. If only frame synchronization is en-
abled, the FIFO can still be used by that channel.
The channel is running.
The FIFO is void of data from any other channel.
The channel is the highest priority channel of those that meet the preced-
ing three conditions.
The third restriction minimizes head-of-line blocking. Head-of-line blocking oc-
curs when a DMA request of higher priority waits for a series of lower priority
requests to come in before issuing its first request. If a higher priority channel
requests control of the DMA controller from a lower priority channel, only the
last request of the previous channel must finish. After that, the higher priority
channel completes its requests through its holding registers. The holding regis-
ters do not allow as high of a throughput through the DMA controller. The lower
priority channel begins no more read transfers but flushes the FIFO by completing
its write transfers in the gaps. Because the higher priority channel is not yet in con-
trol of the FIFO, there are gaps in its access where the lower priority channel can
drain its transfer from the FIFO. Once the FIFO is clear, if the higher priority chan-
nel has not stopped, it gains control of the FIFO.
The DMA FIFO has two purposes:
Increasing performance
Decreasing arbitration latency
For increased performance the FIFO allows read transfers to get ahead of write
transfers. This feature minimizes penalties for variations in available transfer
bandwidth at either end of the element transfer. Thus, the DMA can capitalize on
separate windows of opportunity at the read and write portion of an element trans-
fer. If the requesting DMA channel is using the FIFO, the resources are capable
of sustaining read or write accesses at the CPU clock cycle rate. However, there
may be some latency in performing the first access. The handshaking between
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