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Asynchronous Interface
9.6.4
Asynchronous Writes
9-56
Figure 9–42 shows two back-to-back asynchronous write cycles with the
ARDY signal pulled high (always ready). The SETUP, STROBE and HOLD are
programmed to 2,3,and 1.
At the beginning of the setup period:
J
CE becomes active.
J
BE[3:0] becomes valid.
J
EA becomes valid.
J
ED becomes valid.
J
For the first access, setup has a minimum value of 2. After the first ac-
cess, setup has a minimum value of 1.
At the beginning of a strobe period, AWE becomes active.
At the beginning of a hold period:
J
AWE becomes inactive.
At the end of the hold period:
J
ED goes into the high-impedance state only if another write access to
the same CE space is not scheduled for the next cycle.
J
CE becomes inactive only if another write access to the same CE
space is not scheduled for the next cycle.
For the 'C6201/C6202/C6701, if no write accesses are scheduled for the
next cycle and write hold is set to 1 or greater, then CE stays active for 3
cycles after the value of the programmed hold period. If write hold is set
to 0, then CE stays active ffom four more cycles. This does not affect per-
formance and merely reflects the EMIF's overhead.
For the 'C6211/C6711, the CEn signal goes high immediately after the
programmed hold period.
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